1. Field of the Invention
The present invention relates to a frequency synthesizer, which is capable of outputting signals of a variety of frequencies, to be used for a local oscillator of a transmitter or the like.
2. Description of the Related Art
Heretofore a frequency synthesizer, capable of changing a frequency of an output signal with a predetermined step, has been used for a local oscillator of a transmitter such as a cellular phone. FIG. 8 exemplifies a composition of a conventional PLL (Phase Locked Loop) frequency synthesizer described in "Easy Application Technique of PLL" (Electronic Circuit Know-How, Nippon Hoso Shuppan Association pp. 59), for example.
In FIG. 8, the numerals designate respectively: 10, a reference oscillator; 14, a reference frequency divider; 5, a voltage controlled oscillator; 9, a variable frequency divider; 8, a phase comparator; 6, a loop filter; 11, a controlling circuit for determining a frequency dividing ratio of the variable frequency divider 9; and 12, frequency dividing data from the controlling circuit 11.
In operation, the output from the reference oscillator 10 is divided by the reference frequency divider 14 to generate signals of a reference frequency fr. On the other hand, the output from the voltage controlling oscillator 5 for providing signals of a target frequency fout is divided by the variable frequency divider 9 with a frequency dividing ratio N (N: a positive integer) determined by the controlling circuit 11 so as to be supplied to the phase comparator 8 as a variable frequency divided signal of the frequency fu.
The phase comparator 8 compares the phases of the reference frequency signal and the variable frequency dividing signal to generate a phase comparing signal in accordance with the phase difference between them and to supply it to the loop filter 6. The loop filter 6 extracts the low-band component of the phase comparing signal to generate a frequency controlling voltage V in order to vary the oscillating frequency of the voltage controlling oscillator 5. Accordingly, with such a composition, it is possible to compose a PLL synthesizer in which the phase of the variable frequency divided signal follows that of the reference frequency signal.
Namely, the operation of the PLL synthesizer continues until any phase difference output of delay or advance of the phase comparator 8 disappears and takes a synchronous state when the phase difference becomes zero. At this time, the condition of a relationship of an output frequency fout=N*fr is satisfied, so that it is possible to provide an output of a frequency with the reference frequency as the variation step by varying the frequency dividing ratio N.
In the conventional PLL frequency synthesizer, the phase comparator 8 detects the phase difference of the frequency fr from the reference frequency signal. As a result, the output of the phase comparator 8 contains a frequency component of the reference frequency fr. The PLL synthesizer then needs to set a cut-off frequency of the loop filter 6 to be sufficiently lower than fr in order to eliminate the component of the frequency fr. Setting the cut-off frequency of the loop filter 6 to be lower than fr means, however, that the signals of a frequency higher than that are eliminated so as to restrict the varying speed of the frequency controlling voltage V to fr. Therefore, there has been a disadvantage that it takes too long to synchronize to the target frequency in the case of varying the frequency dividing ratio N in the variable frequency divider 9.